Serial data communications are used to communicate data between various devices. Receiving and correctly decoding a stream of serial data requires the system, including a transmitting device and a receiving device, to be synchronized. Often, a source clock signal, e.g., a Link Symbol Clock with a frequency of either 162 MHz (“reduced bit rate”) or 270 MHz (“high bit rate”), and time stamp information (also referred to herein as “M” and “N”), are included in a stream of serial data transmitted to the receiving device. In these types of systems, an output clock such as a stream clock (also sometimes referred to as a “pixel clock”) having an output frequency that is different than the source clock frequency, e.g., within the range of between 25.175 MHz (such as VGA) and 268.5 MHz (such as WQXGA) at the receiving device must be accurately recovered to increase proper functioning of the system. In certain systems, the time stamp information is 24-bit information is embedded in a data stream from the transmitting device, and relates to the relative frequencies between the source clock and the output clock.
However, because of the frequency disparity between the source clock and the output clock, accurate output clock recovery, also sometimes referred to herein as stream clock recovery (“SCR”), can be difficult with conventional systems. In some systems, the receiving device can perform clock data recovery techniques using a phase locked loop (“PLL”). The PLL analyzes the serial data stream and attempts to synchronize the receiving device with the transmitting device.
Unfortunately, it is a challenge to design a circuit with low-jitter performance that accurately recovers the stream clock since M and N values can be 24-bit values. These types of M and N values imply a typical design solution of an integer-N PLL based recovery circuit, which must have very low bandwidth, e.g., less than 1 Khz for a 270 MHz Link Symbol Clock in an asynchronous mode. Thus, one problem with this conventional type of circuit architecture is that it is rather complex and impractical to design sub-KHz bandwidth in a monolithic system-on-a-chip (“SOC”) integrated circuit.